// Copyright (C) 1953-2022 NUDT
// Verilog module name - mbus_hub 
// Version: V4.1.0.20221212
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         
///////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module mbus_hub
(
        i_clk           ,
        i_rst_n         ,
       
        iv_command      ,
	    i_command_wr    ,
        ov_command_ack  ,
        o_command_ack_wr, 

        iv_command_ack_tse  ,
	    i_command_ack_wr_tse,
        ov_command_tse  ,
        o_command_wr_tse
);
// I/O
// i_clk & rst
input                  i_clk                  ;
input                  i_rst_n                ;      
//nmac data
input      [65:0]      iv_command             ;               
input                  i_command_wr           ;
output reg [65:0]      ov_command_ack         ;
output reg             o_command_ack_wr       ;
             
input      [63:0]      iv_command_ack_tse         ;               
input                  i_command_ack_wr_tse       ;
output reg [63:0]      ov_command_tse         ;
output reg             o_command_wr_tse       ;
//***************************************************
//               command parse
//***************************************************
always @(posedge i_clk or negedge i_rst_n) begin
    if(i_rst_n == 1'b0)begin
        ov_command_tse        <= 64'b0;
        o_command_wr_tse      <= 1'b0;          
    end
    else begin
        if(i_command_wr)begin
            if(iv_command[63:62] == 2'd1)begin//tss/tse
                ov_command_tse[63:62]        <= iv_command[65:64];            
                ov_command_tse[61:58]        <= iv_command[61:58];
                ov_command_tse[57:0]         <= iv_command[57:0] ;
                o_command_wr_tse             <= 1'b1;			
            end   
            else begin
                o_command_wr_tse               <= 1'b0;			
            end
        end      
        else begin
            o_command_wr_tse               <= 1'b0;		
        end
    end
end
//***************************************************
//               command encapsulate
//***************************************************
always @(posedge i_clk or negedge i_rst_n) begin
    if(i_rst_n == 1'b0)begin
        ov_command_ack        <= 66'b0;
        o_command_ack_wr      <= 1'b0 ;    
    end
    else begin
        if(i_command_ack_wr_tse)begin
            ov_command_ack[65:64]        <= iv_command_ack_tse[63:62];
            ov_command_ack[63:62]        <= 2'b01 ;
            ov_command_ack[61:58]        <= iv_command_ack_tse[61:58];
            ov_command_ack[57:0 ]        <= iv_command_ack_tse[57:0] ;
            o_command_ack_wr             <= 1'b1  ;                
        end      
        else begin
            ov_command_ack        <= 66'b0;
            o_command_ack_wr      <= 1'b0 ;               
        end         
    end
end     
endmodule
    